State Machine Correctness Verifier

Analyze this state machine implementation:

{{state_machine_code}}

Expected behavior: {{business_requirements}}

Verify:
1. All states are reachable from initial state
2. All declared transitions are valid and used
3. Dead-end states (if any) are intentional
4. Event handling is exhaustive (no missing cases)
5. Guard conditions prevent invalid transitions
6. Entry/exit actions are idempotent
7. Timeout and error recovery paths
8. Visualize state diagram and transition matrix

Provide test scenarios for edge cases and state coverage.